This application relies for priority, under 35 U.S.C. xc2xa7119, on Korean Patent Application 2001-3677, filed Jan. 26, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a bonding pad structure of a semiconductor device and to a method for fabricating the same. It is particularly applicable to a wafer-level package such as a micro ball grid array (xcexc-BGA).
2. Description of Related Art
As electronic devices become smaller and thinner, there is a growing need to develop smaller and thinner packages as well. In keeping with the current tendency, wafer level packages have experienced significant technological progress. This is particularly true with respect to xcexc-BGA packages, the most commonly used type of wafer level package. In xcexc-BGA packages, a beam lead is formed on a tape, and a metal capillary is then used in a thermo-sonic process to make a direct stitch bonding to a metal pad. Unfortunately, as a result, the bonding pad is subjected to a great deal of impact during the bonding step.
Thus, when conventional basic bonding pad structures (in which first and second metals are in direct contact) are used for a wafer level package (such as xcexc-BGA), the mechanical stress applied during the bonding step deteriorates the adhesion between a metal pad and its underlying layer, an inter layer dielectric (ILD). Delamination between these two layers (metal and dielectric) may cause a metal open failure. To solve this problem, in a new bonding pad designed for a DRAM, a polysilicon layer is contacted beneath the first and second metal pads.
FIGS. 1a through 1f are schematic cross-sectional views of a bonding pad structure illustrating a method of fabricating a bonding pad according to one related method. Referring to FIG. 1a, a first interlayer insulating layer 12 is formed and planarized on a semiconductor substrate 10 having a lower structure including field oxide layers, transistors, capacitors, and so on. A conductive layer pattern such as a P-doped polysilicon layer pattern (P-poly pattern) 14 is formed on the interlayer insulating layer 12 and a second interlayer insulating layer 16 is then formed and planarized on the first interlayer insulating layer 12, including the P-poly pattern 14. The P-poly pattern 14 is introduced to prevent delamination between the first interlayer insulating layer 12 and a first metal pad due to deterioration of the adhesive force between them.
Referring to FIG. 1b, the second interlayer insulating layer 16 is selectively etched to expose a region of the P-poly pattern 14 and form a contact hole h. As illustrated by FIG. 1c, a first metal layer, of an aluminum (Al) or copper (Cu) alloy, is deposited on the second interlayer insulating layer 16 including the contact hole h. The first metal layer is then dry-etched to expose a region of the second interlayer insulating layer 16 surrounding the contact hole h and to form the first metal pad 18 contacting the P-poly pattern 14. The P-poly pattern 14, contacting the first metal pad 18, is metalized by metal diffusion.
Referring to FIG. 1d, an inter-metal dielectric (IMD) is formed and planarized on the second interlayer insulating layer 16, including the first metal pad 18, to provide a third interlayer insulating layer 20. In order to provide an electrical connection with a second metal pad that will be formed later, the third interlayer insulating layer 20 is selectively etched to expose a region of the first metal pad 18, thereby forming a via hole V.
Referring to FIG. 1e, a second metal layer of an Al or Cu alloy is deposited onto the third interlayer insulating layer 20 including the via hole V. The second metal layer is dry-etched to expose a region of the third interlayer insulating layer 20 surrounding the via hole V, thereby forming a second metal pad 22. The second metal pad 22 is electrically connected to the first metal pad 18.
Referring to FIG. 1f, a protective layer 24, having an HDP oxide/PE-SiON deposition structure, is formed on the third interlayer insulating layer 20, which includes the second metal pad 22. The protective layer 24 is dry-etched to open a region of the second metal pad 22 to provide a pad window region W (to which the beam lead will be stitch-bonded). As a result, the first metal pad 18 is in contact with the poly pattern 14, and the second metal pad 22 is in contact with the first metal pad 18. The bonding pad structure is then complete.
In this case, the P-poly pattern 14, placed beneath the metal pad, is made of the same material as the metal pad. This is in contrast to the bonding pad structure in which a metal pad is in direct contact with an interlayer insulating layer. This bonding pad structure thereby improves the bonding characteristic of the layered materials. As a result, it reduces the chances of a metal open failure due to delamination in the bonding beam lead. Unfortunately, however, when the bonding pad is designed and fabricated as described above, the height of the bonding pad is decreased. This increases the step difference between the pad metal, exposed through the pad window region W, and the protective layer 24.
Therefore, although a stronger resistance to external mechanical stress is provided by the contact between the poly pattern 14 and the first and second metal pads 18, 22, the mechanical stress applied to the metal pads during the bonding step actually increases. The sidewall becomes higher in inverse proportion to the height of the bonding pad, thereby reducing the beam lead alignment margin. In other words, a significant step difference between the metal pad and the protective layer 24 increases the external mechanical stress applied to the second metal pad during the bonding process of the beam lead. This problem causes significant quality deterioration such as bonding defects, reduction in the assembly characteristics of semiconductor packages, and so on. Therefore, an urgent demand exists for improvements to solve the problem caused by the large step difference in the foregoing bonding pad structure.
Various aspects and embodiments of the present invention are configured to solve the aforementioned problems. A bonding pad structure according to certain embodiments of the invention, for example, has a greater bonding pad height than the prior art, thereby reducing mechanical stress caused by a step difference between a metal pad and a protective layer and thereby further increasing a misalignment margin.
More particularly, a bonding pad structure of a semiconductor device having multi-layered wires, according to one embodiment of the invention, includes an insulation layer inserted beneath a second metal pad in direct contact with a first metal pad and a lower conductive layer pattern such as P-poly pattern. This configuration increases the height of the bonding pad, without requiring additional process steps. The mechanical stress resulting from a large step difference between a metal pad, exposed through a pad window region, and the protective layer is thus reduced, and a misalignment margin is increased.
According to another aspect of the invention, a contact between the second metal pad, the first metal pad, and the P-poly pattern can be arranged outside the pad window region. The second interlayer insulating layer between the P-poly pattern of the pad window region and the first metal pad is left intact, as well as the third interlayer insulating layer arranged between the first and second metal pads. As a result, the height of the bonding pad at the pad window region increases to the thickness of the remaining layers, thereby reducing a step difference.
The second metal pad is arranged in direct contact with the first metal pad and the P-poly pattern by the insertion of an insulation layer. The contact is made on an external portion of a pad window region, thereby leaving insulation layers between the P-poly pattern and the first metal pad and between the first and second metal pads intact. As a result, the height of the bonding pad is increased to about the thickness of the remaining insulation layers. Mechanical stress applied to the bonding pad is thereby reduced without requiring additional process steps during the packaging process. The step difference between the metal pad and the protective layer, exposed through the pad window region, is also smaller than in the prior art, thereby increasing the misalignment margin.